1. Field of the Invention
The present invention generally relates to semiconductor memory devices and, more particularly, to volatile semiconductor memory devices.
2. Description of the Related Art
The evolution of sub-micron CMOS technology has resulted in an increasing demand for high-speed semiconductor memory devices, such as dynamic random access memory (DRAM) devices, pseudo static random access memory (PSRAM) devices, and the like. Herein, such memory devices are collectively referred to as DRAM devices. Such devices utilize memory cells consisting of one transistor and one capacitor. Due to leakage, the memory cells require periodic refreshing to protect data that is stored in the memory cell from corruption or decaying over time. The data stored in the memory cell is automatically restored to a full logic level when accessed (e.g., via a read or write operation), but must be periodically refreshed when not accessed. Therefore, DRAM devices typically include refresh circuitry to facilitate memory cell refresh.
The amount of time for which a memory cell can retain data without requiring refresh is commonly referred to as the retention time of the cell. Variables in the manufacturing process may result in a broad distribution of retention times for cells within a DRAM device. Testing procedures designed to determine the retention times of cells are often performed as part of the manufacturing process. During these procedures, cells with retention times that fall below a minimum specified retention time (i.e., “weak retention cells”) are identified. In some cases, a manufacturer may offer devices with differing grades, based on different maximum retention time of the cells. For example, cells of a normal grade part may have a lower retention time than a more advanced part. The more advanced grade part may be more desirable, as it requires less frequent refresh operations and, therefore, may consume less standby power. However, cells that have fallen below even the less stringent minimum retention time for normal parts may be considered as having failed.
In some devices, redundancy may be used to replace such failed cells. FIG. 1 illustrates one example of a redundancy scheme utilizing redundant circuitry to replace normal rows 102 having failed cells with redundant rows 104. The replacement may be accomplished by programming programmable read only memory (PROM) registers 106 with the row address of a row with a failed cell, such as row 102F (illustratively having a row address XA). Normal rows with no failed cells are accessed normally, via normal row decoders 111. However, when the normal row XA is accessed (e.g., during a refresh, read, or write operation), the redundant circuitry detects a match with a PROM register 106 and activates a corresponding redundant row 104, via a redundant row decoder 112, instead.
One disadvantage to this redundancy scheme, however, is that the circuitry required to support redundancy (e.g., the redundant rows themselves, the PROM registers, redundant row decoder, and comparison circuitry) occupies a significant amount of chip area, which increases with the number of redundant rows. As a result, only a limited number of redundant rows are typically provided. The advent of portable devices (e.g., cell phones, personal digital assistants, and the like) has brought demands for memory with longer retention times that consume less standby power in order to increase battery life. As a result, the number of weak retention cells may increase beyond the limits of redundancy.
Accordingly, there is a need in the art for improved methods and circuit configurations for utilizing memory cells having weak retention times.